1. Field of the Invention
The present invention relates to a reconfigurable device, a processing assignment method, a processing arrangement method, an information processing apparatus and a control method therefor.
2. Description of the Related Art
There is conventionally proposed a reconfigurable device including even a manufactured LSI circuit apparatus which can change processing contents executed by the circuit by changing an internal circuit configuration. Since it is possible to change the processing of even a manufactured LSI circuit apparatus, there is no need to remanufacture an LSI along with a change in specifications. Such reconfigurable device is currently used in various fields because it is possible to reduce the manufacturing cost or to shorten the development period.
A representative reconfigurable device is mounted with a number of LUTs (Look-Up-Tables) or a number of processing elements. Each element is connected with a switching element such as a multiplexer. Note that settings for operating each structure element such as an LUT, processing element, or switching element are collectively called circuit configuration information. Although there are various methods of generating circuit configuration information, in general, many of them sequentially execute (1) a step of logically assigning processes, which is called technology mapping, (2) a step of physically arranging the processes in respective structure elements, and (3) a step of routing respective structure elements. By executing the three steps, circuit configuration information is finally generated.
In the logical processing assignment step of (1), processes are assigned to structure elements. More specifically, each process is assigned to a logical structure element without specifying a physical structure element. As an index for a sequence change operation, the area of a circuit, an operation speed, or power consumption is generally used. In the arrangement step of (2), a physical assignment, that is, a structure element within the reconfigurable device, which executes each process is determined. Depending on the distance between processing elements where processes having a data input/output relation are arranged, a delay time (maximum operating frequency) significantly changes since the number of switching elements involved in data communication changes. In terms of shortening a delay time, it is generally important to arrange processes having an input/output relation in processing elements which are as close as possible to each other. In the routing step of (3), a route is determined by a switching element for data communication between processing elements having a data communication input/output relation. Since detailed routing is performed as compared with the arrangement step, it is important to determine a route so as to shorten a delay time between the processing elements.
In recent years, along with an improvement in the degree of integration, the scale of processing executable in a reconfigurable device has increased. In addition, requirements on processing itself have become complicated and sophisticated, and therefore, it may be difficult to execute all processes in one reconfigurable device at once. To deal with this problem, there is a method of time-divisionally and sequentially executing processes in one reconfigurable device. More specifically, desired processing is divided, and circuit configuration information corresponding to the divided processes is generated. After that, based on the circuit configuration information, changing operations of the circuit configuration of the reconfigurable device and processes are sequentially executed. This enables to execute large-scale processing in a reconfigurable device. If the circuit configuration is changed every time however, the total processing time is prolonged, thereby deteriorating the speed performance. When the number of divided processes is large, this also causes deterioration of the processing speed.
As a method of solving this problem, there is a multicontext reconfigurable device. A context indicates circuit configuration information, and the multicontext reconfigurable device indicates a reconfigurable device mounted with a memory for storing a plurality of pieces of circuit configuration information. When changing the circuit configuration, it is possible to reconstruct the device by switching the memory, and high-speed switching is possible, thereby significantly shortening the reconstruction time of the circuit. Since it is necessary to mount an additional memory for circuit configuration information, however, the size of the circuit becomes large.
To deal with this problem, Japanese Patent No. 3558119 proposes a method based on a skeleton circuit technique as a method of shortening the reconstruction time. In this method, circuit configuration information called a priority-based circuit is generated in a reconfigurable device in advance. Note that the priority-based circuit indicates circuit configuration information including a common circuit portion common to all of a plurality of pieces of circuit configuration information and a nonexclusive independent circuit portion which is not common to a plurality of circuits and does not share circuit configuration information on the reconfigurable device. By partially reconstructing only a difference of a circuit on the reconfigurable device, a circuit necessary for processing is constructed. As compared with a multicontext type, this method does not increase the circuit size since an additional memory for an arrangement is not needed.
A reconfigurable device may generally execute various kinds of applications, and a common portion is small depending on the applications. The number of pieces of circuit configuration information to be reconstructed changes depending on the applications. In priority-based circuit generation described in Japanese Patent No. 3558119, if a common portion is small, or the number of pieces of circuit configuration information is large and the circuit size of the reconfigurable device is significantly exceeded, it is difficult to efficiently shorten a period for changing the circuit configuration.